Verification Notes (Part 1:Preface)
Preface
When it comes to verification for FPGA (or basically any VLSI in real practice), we’re often provided with two perspectives: block-level verification which checks the functionality of each component that constitutes the IC chip; and fullchip-level verification which examines the entire workflow of the chip.
Block-level verification resembles conventional simulation for any electronic design in the industry. Meanwhile, in order to perform fullchip verification for an FPGA, one has to meticulously go through the whole developing process of the FPGA (functional design through some sort of HDL, RTL synthesis, mapping, adding physical & timing constraints, packing, placing, routing, config-bit generating, etc.)and check for possible bugs throughout every procedure included.
Tools needed include Cadence Virtuoso, HqFPGA(or ModelSim which could serve similar purposes) and of course the little gadget I briefed about in the last post, Perl to facilitate the process.
Outline
Specifically, for block-level verification there are 4 measures that I used in total depending on various scenarios, 2 of which are conducted through Cadence Virtuoso while the other 2 via Verilog.
As for the more complicated fullchip-level verification, I reckon it would be a good choice to first go through the developing process by comparing the operating interface of HqFPGA on Windows and that on Linux(which as a delightful coincidence, are installed respectively on my PC and the computer allocated to me by the company I’m currently working in).